1. Field of the Invention
The present invention is related to integrated circuits incorporating internal timing measurement circuits, and more specifically to techniques for measuring signal delays within an integrated circuit by frequency-stepping a clock signal.
2. Description of Related Art
Measurement of on-chip signal delay is performed routinely in microprocessors in order to determine whether timing windows are maintained and in some cases to measure temperature and power supply voltages indirectly. The limitations of such measurements are typically on the order of one delay stage (one inverter) delay in duration, which in present-day integrated circuits (ICs) is approximately 5 picoseconds (ps). In order to achieve measurement accuracies finer than this, off-chip measurements are generally necessary, but for measuring delays, the errors produced by the signal transit required to bring a signal-under-measurement off-chip typically negate any sort of accuracy improvement that can be had with any off-chip measurement. More accurate techniques s are available to measure delays within integrated circuits, but they typically require complex calibration and/or complex circuits.
Resonant clocking of digital integrated circuits provides low energy consumption and well-controlled clock characteristics, including reduction of jitter and predictable point-to-point delay. In some implementations, a reduced pulse width is employed in resonant clock drivers to further decrease energy consumption, since the clock drive only needs to be active long enough to restore the energy that is lost in the portions (sectors) of the resonant clock distribution network that is being driven by the individual clock drivers.
Mode changing in a resonant clock distribution network is needed for variable operating frequency, for example, in a processor integrated circuit with “turbo” operating modes or in which voltage-frequency scaling is employed to reduce energy consumption when processor activity is low. The mode changing may change operating frequency and/or may change the clock mode from resonant distribution to non-resonant. However, when changing the mode in a resonant clock distribution network, which generally change in the drive strength and/or pulse width of the clock driver circuits, the mode change may generate a short cycle or glitch that can cause improper operation of the integrated circuit in which the resonant clock distribution network is implemented. Changes in mode typically need to generate less than a 1% change in clock period/clock frequency in order to avoid timing margin violations that can result in functional errors. However, a 1% change at a clock frequency of 4 gHz is less than 2.5 ps, which would require at least 1 ps accuracy to measure with any certainty.
It would therefore be desirable to provide a measurement scheme that can be implemented within a microprocessor circuit to determine sub-ps delay values.